Advanced Si-Node Pb-Free Underfill Reliability

Project Statement and Statement of Work for Phase 2

  • Project Statement (Phase 2, Model and Verify with Physical Test Vehicle) (Version 1.3; November 27, 2012)
  • Statement of Work (Phase 2, Model and Verify with Physical Test Vehicle) (Version 1.4; November 27, 2012)

Phase 2 Scope of Work

This project is a continuation of the Advanced Si-Node Pb-Free Underfill Reliability Project. In Phase 1, the project team surveyed industry regarding concerns for underfill performance and reliability. The results of the survey were summarized and published to all iNEMI member companies.

Survey findings and published literature indicate that advanced Si-node flip chip components may see operating conditions where silicon Tj approaches underfill Tg. These components may pass standard JEDEC temperature cycling but fail in the field as a result of power cycling and some combination of transitional underfill thermal mechanical properties. Phase 2 will:

  • Use modeling to define limits for key structural variables and thermal mechanical testing ranges.
  • Identify physical test vehicle materials sources and design experiment based on modeling results.
  • Select a set of common underfills having predetermined Tg, and modulus values and fully characterize their thermal mechanical behavior.
  • Perform testing on the physical test vehicles using both standard and model defined power cycling routines to determine reliable lifetimes.
  • Report results and further recommendations for test standard revisions and or design guidelines.

Background

Advanced Si nodes (40nm and below) run at increasingly higher Tj. As Tj approaches the underfill Tg, flip chip stress distribution changes radically. At temperatures between Underfill Tg and Substrate Tg all Si/substrate CTE mismatch and warpage stress is carried through the bump structure and potentially fragile silicon ELK layers.

Current qualification criteria and standards are not adequate to predict long-term reliability for Advanced Si nodes where Tj often can exceed the underfill Tg. Testing does not consider applications where Tj exceeds Tg in combination with ELK (extra low K) and Pb-free bump requirements.

Overall Project Focus

This project will:

  • Examine the long-term reliability of advanced Si-node FCBGA devices in instances where the underfill Tg is in close proximity to the silicon Tj. In particular, the project will focus on devices where application power cycling may produce temperature cycling effects that significantly challenge the JEDEC standard requirements for temperature cycling.
  • In Phase 1 (completed), the project team conducted a review and analysis of existing literature and standard practices related to the selection of underfill material properties. The investigations provided the information necessary to design an experimental test vehicle and develop a testing routine that will be used in the project’s second phase.
  • Phase 2 of this project will evaluate the performance of a standard temperature cycle test routine against an experimental routine that would be tailored to more closely approximate the actual temperature conditions experienced by a device in a high duty cycle environment.
  • Depending on the outcome of testing, a third phase of this project would consider either preparing a set of package design guidelines for underfill property selection or develop a supplemental environmental testing standard for package configurations where duty cycle demands may create a significant reliability risk.

Benefits

Participants in the project and the industry at large stand to benefit in the following ways:

  • Greater understanding of how material selection and end use conditions impact the long-term reliability of flip chip BGAs.
  • Potential generation of environmental testing standards and/or design guidelines to be applied in cases when use and packaging requirements create a situation where silicon Tj approaches or exceeds the Tg of the flip chip underfill.
  • Quantification of the actual reliability performance ranges of components that are designed with these Tj/Tg relationships.

Steps for Joining the Project

Please note: iNEMI membership is required to participate in this project. The period for becoming a founding member for this project will close on February 15, 2013.  The project will officially begin as soon as two iNEMI members sign the Project Statement.

For iNEMI members:

  • Complete and sign the project statement
  • Fax the completed statement(s) to +1 (703) 834-2735 or scan and email to infohelp@inemi.org

For non-members:

For Additional Information

Haley Fu
+86 21-2215 7746 (China)
haley.fu@inemi.org
 

Chair: Robert Carson, Cisco
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