Board Coplanarity in SMT

Click here for OEM/ODM Assistance Request for Dynamic Warpage of your PCBs

End-of-Project Webinar

The iNEMI member only webinar was held on August 23, 2011.

Project Objective

Develop recommendations for measuring board land coplanarity during reflow to ensure high-quality, high-yield SMT process for the next generation of BGA components and boards. The team will also work with IPC to create standards based on these recommendations.

Background

The current specifications for component lead coplanarity and board bow and twist have not kept pace with developments in packaging and board technologies. Some system manufacturers are experiencing poor SMT yields using materials that meet the current specifications.  The converse is also true. Some of the newest component technologies are hampered as they fail to meet the current component standards, but have demonstrated high yields in SMT.  It is clear that updated standards are needed to provide the necessary assurance of quality without impeding the continuous innovation on which the electronics industry is based.

New measurement techniques have enabled the measurement of flatness during simulated SMT conditions, allowing more directly relevant standards to be developed.  Several standards bodies have already issued specifications for using these techniques in components.  This iNEMI project will focus on extending these new techniques to ensure the flatness of system boards as well.

Deliverables

Phase 1

  • Metrologies and recommendations to enable measurement and specification of board land coplanarity.
  • Establish a quantifiable baseline for board coplanarity and verify the need for a dynamic warpage methodology.
  • Quantify the level of coplanarity over a large range of board thicknesses, form factors and BGA sizes at simulated assembly temperatures to set requirements for differing board technologies and categories.
  • Recommend acceptance criteria for board flatness and conditions for sampling and measurement requirements.

Phase 2

  • Reconcile board and component requirements with JEDEC and JEITA, and ensure that limitations of board manufacturing process are comprehended in all relevant standards.

Additional Materials

  • Presentation: Implementing High Temperature Coplanarity Requirements for Components and PWBs (PDF)
  • Statement of Work (Version 5.0, May 8, 2008)
Chair: John Davignon, Intel
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