1st Level Interconnect Void Characterization

Project Leader:
Kor Oon Lee (Intel)

Project Co-Leader: Sze Pei Lim (Indium)

Project Co-Leader: Kiyoshi Ooi (Shinko)


End of Project Webinar - members only

Session 1 (APAC)
Thursday, June 16, 2022
10:00-11:00 a.m. JST (Japan)
9:00-10:00 p.m. EDT on June 15 (Americas)
Register for this webinar
Session 2 (Americas & Europe)
Thursday, June 16, 2022
9:00-10:00 a.m. EDT (Americas)
3:00-4:00 p.m. CEST (Europe)
10:00-11:00 p.m. JST (Japan)
Register for this webinar

SOW & Project Statement

Statement of Work (v1.0; October 31, 2019
Project Statement (v2.0; October 31, 2019)


Flip chip packages are key solutions that help drive high-density and improved interconnect for advanced electronics packaging. However, the formation of small voids (micro voids) can occur in solder-based flip chip joints during the assembly process, and these voids tend to grow after multiple reflows (solid-liquid-solid). Micro voids in 1st level interconnect materials can be a concern for applications that involve high electrical and thermal flux across the flip chip. Voids can have an impact on electromigration in the joint, adversely affecting the reliability of the electrical interconnect.
X-ray is the preferred method of inspection for voids; however, the small dimension of the flip chip bond and the interference of substrate and die metallization make it challenging to accurately locate and measure the size of the voids or percentage of voiding. There are currently no guidelines or standards that define an acceptable percentage of voiding or how the percentage of voiding relates to the reliability of the assembly.

Project Purpose

This project will study voids in flip chip interconnect to determine their location and volume. It will also seek to understand how voiding in 1st level interconnect affects product reliability and what level of voiding is acceptable while maintaining reliability requirements. The project will have two distinct phases:
  • Study and determine recommended inspection capabilities for micro-voids in 1st level interconnect materials
  • Study the relationship between voids and the electrical and mechanical reliability of the assembly
The project is expected to develop technical guidelines regarding acceptable voiding characteristics for flip chip interconnects that can be shared with Industry and relevant standards bodies.


Voids in First-Level Interconnects and Their Impact to Solder Joint Reliability,” Kor Oon Lee, Intel, Session WA1-3: iNEMI Session, May 11, 2022, 2022 International Conference on Electronics Packaging (ICEP 2022)
Phase 1 Project Report Webinar (February 3 & 4, 2021)

Call-for-participation webinar (December 12, 2019)

Further Information

Contact: Masahiro Tsuriya (m.tsuriya@inemi.org)