2023 Project Leadership Awards


Award Criteria

The iNEMI Project Leadership Award is a team award and recognizes the team members and the iNEMI projects that deliver in the any of the following areas: 
  • Superior performance of electronics manufacturing practices  
  • Superior technology and business results 
  • Positive impact on the electronics manufacturing value chain and its ecosystem 

2023 Winners

1st Level Interconnect Void Characterization Project

Flip chip packages are key solutions that help drive high-density interconnect for advanced electronics packaging. However, the formation of small voids (micro-voids) can occur in solder-based flip chip joints during the assembly process and can be a concern for applications that involve high electrical and thermal flux across the flip chip. Voids can have an impact on electromigration in the joint, adversely affecting the reliability of the electrical interconnect. X-ray is the preferred method of inspection for voids; however, the small dimension of the flip chip bond and the interference of substrate and die metallization make it challenging to accurately locate and measure the size of the voids or percentage of voiding. 

1st Level Interconnect Void Characterization project addressed the need for guidelines regarding how the percentage of voiding relates to the reliability of the assembly and to define what level of voiding is acceptable while maintaining reliability requirements. The project had two phases:
  • Phase 1: Study the inspection capability of X-ray equipment to detect micro-voids and determine recommended inspection capabilities for micro-voids in 1st level interconnect materials.
  • Phase 2: Study the impact of voids on solder joint reliability and identify/understand failure modes. Provide recommendations to the industry on acceptable voiding characteristics for packaging reliability.

The project team developed process recipes to consistently build test packages with and without solder voids; ran thermal shock, temperature cycling and electromigration tests to study the impact of voids on solder joint reliability; and performed failure analyses to understand failure modes and provide recommendations for the industry. Project findings were presented in conference papers at ICEP 2021 and 2022, ECTC 2022, IMAPS 2022 and IMPACT 2022. The team received Outstanding Paper recognition from the ICEP 2022 conference.

Team Members 

Kor Oon Lee, Intel (Project Leader)
Sze Pei Lim, Indium (Co-leader)
Kiyoshi Oi, Shinko (Co-leader)

Hiromi Fujii, AIST
Koyuki Kawakami, Shinko
Steven Martell, Nordson
Kei Murayama, Shinko
Takahiro Nishimura, Nihon Superior
Toshiaki Ono, Nordson
Haruo Shimamoto, AIST
Keith Sweatman, Nihon Superior
Yvonne Yeo, IBM


5G/mmWave Materials Assessment & Characterization Project

Next-generation 5G communications solutions require ultra-low loss laminate materials and PCBs/substrates for efficient design and manufacturing. However, these materials pose challenges. For example, there is no consistent methodology for measuring transmission loss or Df/Dk, especially for higher frequencies (e.g., >30 GHz). Many approaches are currently used, requiring different fixtures and test methods, sample preparation, and/or data analysis/extraction. 

The goal of the 5G/mmWave Materials Assessment and Characterization project was to develop a guideline/best practice for a standardized measurement and test methodology that can be shared with industry and relevant standards organizations. The initial focus was to benchmark current available test methods and provide pro/con analysis, identify gaps (if any) for extending test methods to 5G/mmWave frequencies, as well as develop reliable reference standard materials for set-up and calibration.

This project involved the entire electronics value chain, bringing the ecosystem together to solve critical next-generation problems. Participants included end users, material and equipment suppliers, and universities and national labs. The project team published three in-depth reports:
  1. Benchmark Current Industry Best Practices for Low Loss Measurements 
  2. Benchmark Emerging Industry Best Practices for Low Loss Measurements 
  3. A Round Robin Study to Determine Measurement Accuracies of Commercial Resonator-Based Techniques 
Results were also reported in a series of four iNEMI-sponsored 5G/mmWave Tech Topic webinars and in presentations at 12 international conferences in 2019, 2021 and 2022.

Team Members

Project Co-leaders:
Say Phommakesone,  Keysight Technologies
Richard Stephenson, EMD Group
Dr. Chang-Sheng Chen, ITRI

AGC-Nelco  Keysight Technologies
AT&S MacDermid Alpha
Centro Ricerche FIAT-FCA Mosaic
EMD Group Nokia
Flex Panasonic
Georgia Tech QWED
Hitachi Chemical (Resonac) Sheldahl 
Ibiden Shengyi 
IBM Unimicron
Intel Wistron 


High Density Interconnect Socket Warpage Predictions & Characterization Project, Phase 1

Socket connectors are getting larger (>50x50mm), and density continues to increase, creating challenges in socket warpage simulation and control and adding even more challenges to SMT assembly processes in terms of yield and performance. This project investigated warpage of high-density large size array sockets and the impact of socket design and fabrication process on warpage. In particular, the project aimed to:
  • Develop socket warpage measurement guidelines and prediction methods
  • Determine the impact of molding and design on large size socket warpage
  • Reduce the impact of socket warpage on PCBA yield and reliability
  • Improve socket flow and warpage simulation time to reduce design cycles for future generation sockets

Few studies have been conducted in the field of ball grid array (BGA) socket warpage management. The High Density Interconnect Socket Warpage Prection & Characterization project explored novel simulation techniques to speed up the flow prediction by simulation and reduce physical experiments needed to improve the time-to-market (TTM) cycle of high-density interconnect (HDI) sockets. The team worked from very fundamental basics to the application of numerical simulations to improve the socket design cycle; established an analysis and validation framework for socket development; and investigated the impact of socket design, fiber filled material properties and molding process conditions on socket warpage. 

The project outcome allows faster flow and warpage simulation for HDI socket design and development. The utilization of numerical predictions was increased, and material cost used for design prototyping and injection mold chase tape-outs was reduced. Simulation software partners from the project tested proof of concepts of the simplification and new features made it to commercial version of the software for more time-efficient predictions.

Benefit / value to iNEMI project participants:
  • Material partners gained in-depth understanding on how their LCP properties can be better described in industrial software simulation settings. They also gained exposure to how their material behaves in the field when conducting injection molding at our socket partners sites.
  • Socket partners gained exposure to new LCP material grades and how to optimize the injection process with the help from material partners.
  • Software partners had the opportunity to fine tune their material databases with actual samples from our software partner and validate the simulation models from socket partner’s data. The opportunity to evaluate the simplification POC also enabled new features in their latest software release. 
  • Measurement partners also gained opportunity to conduct dynamic warpage measurements and develop best practices for consistent techniques in the project. 

Team Members 

Renn Chan Ooi, Intel (Project Leader)

Allen Cheng, FIT
Ethan Chiu, Moldex3D
Stephen Chiu, Lotes
Franco Costa, Autodesk
Ryan Curry, Akrometrix
Darwin Fan, Celanese
Andrew Gattuso, FIT
Sam Hsieh, Moldex3D
Currey Hsieh, Lotes
Wei Keat Loh, Intel
John Thompson, Amphenol
Jefferey Toran, Amphenol 
Pierre-Louis Toussaint, Insidix
YongFu Wang, Lotes
Wendy Xu, Celanese 
Dave Yu, Celanese