High Density Interconnect Socket Warpage Prediction and Characterization, Phase 1
Section: Board Assembly

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Project Leader

Chair: Renn Chan Ooi, Intel Corporation


End of Project: HDI Socket Warpage


Call for Participation: Warpage Characterization and Management Program


Statement of Work & Project Statement



In electronics products, many types of socket connectors are application specific. Today’s high speed, solder array-based socket connectors are complex components. High density interconnect sockets are growing in dimension due to the increased pin counts in flip chip land grid array (FCLGA) products such as CPUs and GPUs. Any warpage across the sockets adds even more challenges to the SMT assembly processes in terms of yield and performance, as well as rework. There are not many studies published on the socket warpage issue. Dynamic warpage measurement techniques are available but are challenging for sockets due to the increased complexity and variety of design and form factor of sockets, especially under reflow temperature profiles. 


This project, which is part of the Warpage Characterization and Management Program, will investigate the warpage of high-density large size array sockets and the impact of socket design and fabrication process on warpage.  In particular, the project aims to: 

  • Develop socket warpage measurement metrology and prediction methods
  • Determine the impact of molding and design on large size socket warpage
  • Investigate mitigation approaches for improved SMT performance


Warpage is a multi-physics and holistic issue which involves materials, design and manufacturing processes. Participation of researchers and engineers from package designers and manufacturers, EDA and simulation tool providers and equipment suppliers for warpage measurement, as well as industrial organizations and academic institutes, is required. We welcome participation from the industry. 
Please refer to the project SoW for more information. 


Haley Fu (haley.fu@inemi.org)