Low Temperature Material for First Level Interconnect Task Force
Section: Packaging

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Project Leaders

Chair: Sze Pei Lim, Indium

Co-Chair: Dr. Charles Arvin, IBM

Task Force Report on Low Temperature Material for First Level Interconnect 

The Low Temperature Materials for First Level Interconnect Task Force reviewed material and process options currently available or under development to determine whether low temperature materials (LTM) being used in other levels of electronics assembly could also be used for first level interconnects. Options were assessed on the basis of their compatibility with the interfaces that have to be connected and the operating conditions to which they are likely to be exposed in integrated circuit packages.

The Task Force conducted a literature review as well as an industry survey. The information resulting from these efforts were reported in a webinar and a white paper published by the Task Force (see links below). Conclusions drawn from this information were used to define a new project — Low Temperature Material Discovery and Characterization for First Level Interconnect, which will launch in spring of 2023.

Webinar presentation: Report on Low Temperature Interconnects in First Level Packaging (includes link to recorded webinar)
June 28, 2022

White paper: Low Temperature Materials for Packaging First Level Interconnect (iNEMI members only; requires log-in
August 1, 2022


  • The increased size of IR detector arrays is a result of a better understanding of crystal growth techniques, better photolithography, and cleaner processing environments, all transferred from silicon foundries to the “exotic” semiconductors used for IR detectors.
  • Factors that are driving the electronics industry toward lower process temperatures are also having an impact on the 1st level interconnects that interface between the increasingly complex processors and the circuitry that relies on those processors for delivering the functionality on which modern society is now so dependent. One factor is the need to reduce the energy consumption in electronics manufacturing for economy and environmental protection.  
  • Lower process temperatures also make it possible to use cheaper, and sometimes more environmentally friendly materials, in electronic assemblies that would be degraded by the temperatures required in processes based on the current generation of lead-free solder alloys.   
  • Other temperature-related factors are warpage reduction, especially for very thin packages, and the need for a solder melting point hierarchy for multiple reflow processes. 
  • For first level interconnects, however, the overriding concern is the temperature sensitivity of advanced semiconductor devices. Increasing demands placed on those interconnects are forcing manufacturers to explore novel materials and processes such as transient liquid phase sintering (TLPS) materials, sinterable silver and copper pastes, and direct copper-to-copper bonding. 
  • Commonly available low melting temperature alloys such as tin-bismuth and tin-indium alloys, as well as novel low melting point alloy systems, are also under consideration.  
  • Since they play an important role in first level interconnects, consideration also has to be given to other assembly materials, such as conductive and non-conductive adhesives, and underfills that can be cured at lower temperatures.

Task Force Focus

It is only relatively recently that serious consideration has been given to the use of low temperature processes for first level interconnect and the published literature is limited. To fill that gap iNEMI conducted a market survey to determine current usage of low temperature materials for first level interconnect. The information provided a basis for determining whether the use of low temperature materials can be extended to other advanced packaging technologies. Specifically, the survey:
  • Identified the challenges and requirements in key application sectors such as photonics, quantum computing, high performance computing, artificial intelligence, servers, sensors and LED luminaires. 
  • Gathered information from substrate and material vendors on the materials that are available to meet these challenges.
The Task Force published a white paper that takes into account the particular requirements of each application, recognizing the need for different materials characteristics and different measures of reliability. These needs are matched with the materials and processes that vendors are currently offering, and areas where further development is required were defined.  The white paper:
  • Defines material properties characterization required for successful application to first level interconnect 
  • Proposes potential application for low temp solders 
  • Identifies the challenges of low temp solder use and its application
  • Provides data-based guidance on the selection of interconnect materials that can deliver an overall reduction on the processing temperature required in the first level construction of IC package.


Low Temperature Material for 1st Level Interconnect in Semiconductor Packaging,” Sze Pei Lim, Indium Corporation, Electronics Packaging Technology Conference (EPTC), December 9, 2022; Singapore) (members only; requires log-in)

Low Temperature Interconnects in 1st Level Packaging and its Challenges,” Charles Arvin, IBM, Session WA1-4: iNEMI Session, May 11, 2022, 2022 International Conference on Electronics Packaging (ICEP 2022)

Low Temperature 1st Level Interconnect in Packaging and Its Challenges,” presented by Sze Pei Lim (Indium), iNEMI Session at ICEP, May 13, 2021  (virtual event)  


Masahiro Tsuriya (m.tsuriya@inemi.org)