Advancing Manufacturing Technology

PCB Warpage Characterization and Minimization Project
Sunday, May 31, 2020
Section: Board Assembly TIG

Project Leaders

Srinivas Aravamudhan, Intel

End-of-Project Webinar

Project Statement and Statement of Work


Customer demands for smaller form factor electronic devices are driving the use of thinner electronic components and thinner printed circuit board (PCB) in the assembly process. The use of thinner components and thinner multi-up panel PCBs (≤ 40 mils) has led to PCB warpage issues in the surface mount (SMT) assembly process, which in turn impacts the PCB assembly yield. PCBs with excessive warpage impact paste print quality in print process and solder joint formation during reflow soldering leading to SMT assembly defects. Lack of industry standard for PCB warpage at reflow temperature further compounds the PCB warpage risk to SMT assembly yield. 

Project Purpose

This iNEMI project will help to explore the three vectors (PCB fabrication process, PCB design and Board assembly process conditions) and develop guidelines for each of these vectors which will help to minimize PCB warpage and improve SMT margin/yield to the benefit of participants.


Additional Information

Haley Fu