PCB Warpage Characterization and Minimization Project
- Presentation from end-of-project webinar (May 13 & 14, 2020)
Project Statement and Statement of Work
Customer demands for smaller form factor electronic devices are driving the use of thinner electronic components and thinner printed circuit board (PCB) in the assembly process. The use of thinner components and thinner multi-up panel PCBs (≤ 40 mils) has led to PCB warpage issues in the surface mount (SMT) assembly process, which in turn impacts the PCB assembly yield. PCBs with excessive warpage impact paste print quality in print process and solder joint formation during reflow soldering leading to SMT assembly defects. Lack of industry standard for PCB warpage at reflow temperature further compounds the PCB warpage risk to SMT assembly yield.
This iNEMI project will help to explore the three vectors (PCB fabrication process, PCB design and Board assembly process conditions) and develop guidelines for each of these vectors which will help to minimize PCB warpage and improve SMT margin/yield to the benefit of participants.
- End-of-project webinar (May 13 & 14, 2020)
- Impact of PCB Manufacturing, Design, and Material to PCB Warpage, presented by Antonio Caputo (Intel Corporation), Technical Session: Design for Manufacturability, IPC APEX EXPO, February 4, 2020 (San Diego). Paper Presentation
- Call for participation presentation (June 14/15/2017)
- Call for participation presentation (March 15/16, 2017)