1st Level Interconnect Void Characterization, Phases 1 & 2
Section: Packaging

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Project Leaders

Project Leader: Kor Oon Lee, Intel

Project Co-Leader: Sze Pei Lim, Indium

Project Co-Leader: Kiyoshi Ooi, Shinko

2023 Project Leadership Award

Congratulations to the 1st Level Interconnect Void Characterization project team for receiving a 2023 iNEMI Project Leadership Award. These awards recognize projects that have demonstrated superior performance of electronics manufacturing practices, provided solutions that enable significant technology and business results and/or had a positive impact on the electronics manufacturing value chain and its ecosystem. The project team members are:
  • Kor Oon Lee, Intel (Project Leader)
  • ​Sze Pei Lim, Indium (Co-leader)
  • Kiyoshi Oi, Shinko (Co-leader)

  • Hiromi Fujii, AIST

  • Koyuki Kawakami, Shinko

  • Steven Martell, Nordson

  • Kei Murayama, Shinko

  • Takahiro Nishimura, Nihon Superior

  • Toshiaki Ono, Nordson

  • Haruo Shimamoto, AIST

  • Keith Sweatman, Nihon Superior
  • Yvonne Yeo, IBM

End-of-Project Webinar


Statement of Work & Project Statement

Statement of Work (v1.0; October 31, 2019)
Project Statement (v2.0; October 31, 2019)


Flip chip packages are key solutions that help drive high-density and improved interconnect for advanced electronics packaging. However, the formation of small voids (micro voids) can occur in solder-based flip chip joints during the assembly process, and these voids tend to grow after multiple reflows (solid-liquid-solid). Micro voids in 1st level interconnect materials can be a concern for applications that involve high electrical and thermal flux across the flip chip. Voids can have an impact on electromigration in the joint, adversely affecting the reliability of the electrical interconnect.
X-ray is the preferred method of inspection for voids; however, the small dimension of the flip chip bond and the interference of substrate and die metallization make it challenging to accurately locate and measure the size of the voids or percentage of voiding. There are currently no guidelines or standards that define an acceptable percentage of voiding or how the percentage of voiding relates to the reliability of the assembly.

Project Purpose

This project will study voids in flip chip interconnect to determine their location and volume. It will also seek to understand how voiding in 1st level interconnect affects product reliability and what level of voiding is acceptable while maintaining reliability requirements. The project will have two distinct phases:
  • Study and determine recommended inspection capabilities for micro-voids in 1st level interconnect materials
  • Study the relationship between voids and the electrical and mechanical reliability of the assembly
The project is expected to develop technical guidelines regarding acceptable voiding characteristics for flip chip interconnects that can be shared with industry and relevant standards bodies.



Masahiro Tsuriya (m.tsuriya@inemi.org)