1st Level Interconnect Void Characterization, Phases 1 & 2
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End-of-Project Webinar
1st Level Interconnect Void Characterization Project, Phase 2 (June 15 & 16, 2022)
Statement of Work & Project Statement
Background
Flip chip packages are key solutions that help drive high-density and improved interconnect for advanced electronics packaging. However, the formation of small voids (micro voids) can occur in solder-based flip chip joints during the assembly process, and these voids tend to grow after multiple reflows (solid-liquid-solid). Micro voids in 1st level interconnect materials can be a concern for applications that involve high electrical and thermal flux across the flip chip. Voids can have an impact on electromigration in the joint, adversely affecting the reliability of the electrical interconnect.
X-ray is the preferred method of inspection for voids; however, the small dimension of the flip chip bond and the interference of substrate and die metallization make it challenging to accurately locate and measure the size of the voids or percentage of voiding. There are currently no guidelines or standards that define an acceptable percentage of voiding or how the percentage of voiding relates to the reliability of the assembly.
This project will study voids in flip chip interconnect to determine their location and volume. It will also seek to understand how voiding in 1st level interconnect affects product reliability and what level of voiding is acceptable while maintaining reliability requirements. The project will have two distinct phases:
X-ray is the preferred method of inspection for voids; however, the small dimension of the flip chip bond and the interference of substrate and die metallization make it challenging to accurately locate and measure the size of the voids or percentage of voiding. There are currently no guidelines or standards that define an acceptable percentage of voiding or how the percentage of voiding relates to the reliability of the assembly.
Project Purpose
This project will study voids in flip chip interconnect to determine their location and volume. It will also seek to understand how voiding in 1st level interconnect affects product reliability and what level of voiding is acceptable while maintaining reliability requirements. The project will have two distinct phases:
- Study and determine recommended inspection capabilities for micro-voids in 1st level interconnect materials
- Study the relationship between voids and the electrical and mechanical reliability of the assembly
Presentations
- “The Effects of Voids on Solder Joint Reliability in First Level Interconnect,” presented by Sze Pei Lim (Indium), representing iNEMI’s 1st Level Interconnect Void Characterization project, International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT), Session S12: Advanced Bonding and Interconnect Technology, October 27, 2022 (Taipei, Taiwan).
- 1st Level Interconnect Void Characterization Project, Phase 2 End-of-Project Webinar (June 15 & 16, 2022)
- “Voids in First-Level Interconnects and Their Impact to Solder Joint Reliability,” Kor Oon Lee, Intel, Session WA1-3: iNEMI Session, May 11, 2022, 2022 International Conference on Electronics Packaging (ICEP 2022)
- “Voids Inspection Capability Study in First-Level Interconnections for Flip Chip Packages,” presented by Kor Oon Lee (Intel), iNEMI Session at ICEP, May 13, 2021 (virtual event)
- Phase 1 Project Report Webinar (February 3 & 4, 2021)
- Call-for-participation webinar (December 12, 2019)