Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology, Phase 2
- Phase 2 End-of-Project & Phase 3 Call-for-Participation Webinar — public version (March 5, 2020)
- Phase 2 End-of-Project & Phase 3 Call-for-Participation Webinar — member version (March 5, 2020)
Statement of Work and Project Statement
- Integrated SiP packages are becoming more popular as an electronic packaging solution. This package type requires finer circuit patterns designs. However, optical inspection has limitations in detecting the defect features, such as: a) Line width violations; b) Spacing violations; c) Excess copper or missing copper; d) Short or open circuits; e) Cuts; f) Holes; g) Via bottom integrity; h) line neck down; and i) micro bump shape and bump shear strength performance.
- Inspection limitations impact yield assessment and quality validation on the substrate/boards which will be used for integrated SiP packages.
- Inspection capability on fine line (<10um) and space (<10um) on the panel size substrates/board impacts both yield and performance capability. Fine line and space requirements provide high density interconnects which supports the high I/O high bandwidth memory and other component integration of fine pitch memory, and other fine pitch devices.
- iNEMI started this project in 2016. Phase 1, Fine Circuit Pattern Inspection Metrology, which included an industry-wide survey to assess the measurement and inspection capability and readiness for fine circuit pattern substrates, was completed in February 2017. Detailed analysis on industry capability and key recommendations are available as the results of Phase 1.
- The team decided to move to the next phase to conduct the inspection capability study on the fine pitch patterns which are less than 10um line space with various defects patterns based on the key recommendations from Phase 1.
Purpose of Project
The current project is a continuation from Phase 1. The purpose of this current project is to further characterize and quantify industry capability by conducting inspection capability study and analysis using test vehicles (TV) with line space features and defect patterns.
- Design and fabrication of glass test vehicle has been executed as the pre-work for Phase 2. A defect pattern design with 7 different line widths is fabricated on wafer form to materialize the Test Vehicle.
- Defect patterns includes a) Line width violations; b) Spacing violations; c) Excess copper or missing copper; d) Short or open circuits; e) Cuts.
- Line widths are designed with10um, 8um, 6um, 4um, 3um, 2um, 1um.
- Inspection / Metrology Evaluation of Fine Pitch Test Vehicles for Advanced Packages
Presenter: Masahiro Tsuriya (iNEMI)
iNEMI Session at ICEP 2019
April 17, 2019 / Niigata, Japan
- Call for Participation Webinar
- Presentation (November 1, 2017)
- Phase 1: Fine Pitch Circuit Pattern Inspection/Metrology
- Phase 3: Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology
Further InformationMasahiro Tsuriya