Advancing Manufacturing Technology

Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology, Phase 3
Section: Packaging

Project Leaders

Feng Xue, IBM

Joe Zou, Intel

Charlie Reynolds, IBM

Call-for-Participation Webinar 

Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology Project, Phase 3 Call-for-Participation Webinar (March 5 2020)

Statement of Work and Project Statement 


  • The finer pitch substrate features used in new advanced packaging technologies such as SiP, 2.5D, etc., can make it difficult to validate designs and, as a result, impact yield assessment and quality validation of these new packages. There is a need to identify and characterize the capabilities of inspection technologies that can enable faster process development and higher yield in volume production. The Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology project was organized to address this need.

Phase 3 Focus

Phase 3 continues the study of inspection technologies begun in Phase 2, focusing on an organic test vehicle (TV).

  • Evaluate current inspection & measurement capabilities for fine pitch substrates that will be needed over the next five years.
  • Fabricate TV on organic substrate with the same TV designs used in Phase 2.
  • Understand and quantify the automatic optical inspection (AOI) capability limitations for the fine pitch patterns and defects on TVs.
  • Compare with other metrologies, such as SEM or OGP, and identify the different capability results among the TV substrate.
  • Start the review of TV designs and defect modes for 10um line/space down to 1um and determine implications for organic substrate fabrication. 
  • Over the longer term, analyze measurement data and compare the data with AOI-type equipment and other metrologies and TV substrate types. 

Previous Related Projects

Fine Pitch Circuit Pattern Inspection/Metrology, Phase 1
Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology, Phase 2

Further Information

Masahiro Tsuriya