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Statement of Work and Project Statement
- Statement of Work (Version 1.0; July 10, 2017)
- Project Statement (Version 1.0; July 10, 2017)
Background
The iNEMI packaging workshop held in Japan in 2009 clearly identified problems with the existing warpage evaluation criteria for organic package assembly to printed circuit boards. 2013 iNEMI Roadmap described package warpage as one key challenge. Packaging technology is aggressively evolving to meet new user demands and requirements. Dynamic warpage characteristic of electronic package is critical for seamless board assembly. Hence this effort is to understand the kind of dynamic warpage demonstrated in industry. The project has accomplished 3 phases addressing metrology challenges and the recent trends of package warpage characteristics. The study and outputs of earlier phases can be found at iNEMI project webpage.
The project team has gained significant learning about different package technology dynamic warpage behavior and its comparison to existing industry standards and it gives a different perspective of how packages can react differently to temperature. The project team believes that the variety of packages considered earlier has not encompassed what is available in the market and hence the team decided to continue with the effort.
Project Purpose
- Characterize emerging electronic packaging technology dynamic warpage behavior to develop a better understanding of the current development of package construction and material development, for example:
- Silicon Interposer and Embedded Silicon Bridge (EmIB) with different package stiffeners and constructions.
- Next generation of POP packages that leverages wafer level process for package construction which include Panel and Wafer level molding. These also include the use of new fiber reinforced mold material for warpage control.
- System In Package/Multi Chip Package (BGA) with different configuration and layout.
- Embedded Package (embedded silicon, actives and passives).
- Based on previous work and the possibility to collaborate with the Low Temp Solder Project to assess the following:
- To assess the impact of lower temperature solder on package warpage for those packages collected in Phase 2 and 3.
- To establish the risk level based on package technology with respect to warpage only.
- Collaborate with FEA supplier to establish some design sensitivity study to optimize dynamic warpage for each package technology.
Presentations
- PCB Warpage Characterization and Minimization, presented by Mike Huang (Wistron), IMPACT-EMAP 2020, October 21-23, 2020; Taipei, Taiwan and online.
- Predictive Modelling Methodologies for Bi-material Strip Warpage, presented by Jenn An Wang (CoreTech System / Moldex3D), IMPACT-EMAP 2020, October 21-23, 2020; Taipei, Taiwan and online. Paper Presentation
- Predictive Modelling for Bi-material Strip Warpage, presented by Kang Eu Ong (Intel), September 30, 2020 — This webinar updated simulation results for Phase 4 of the Warpage Characteristics of Organic Packages project. The team has conducted further simulations to study cure shrinkage properties and post mold cure (PMC) process.
- End-of-Project Webinar presentation, September 18 & 20, 2019 (members only; requires log-in)
- Impact of Low Temperature Solder on Electronic Package Dynamic Warpage Behavior and Requirements, presented by Wei Keat Loh (Intel Malaysia), ECTC 2019, May 29, 2019, Las Vegas, Nevada Paper Presentation
- Molded Electronic Package Warpage Predictive Modelling Methodologies, presented by Wei Keat Loh (Intel Malaysia), iNEMI Session at ICEP 2019, April 17, 2019, Niigata, Japan Paper Presentation
- Modeling of Molded Electronic Package Warpage Characteristic with Cure Induced Shrinkage and Viscoelasticity Properties, presented by Wei Keat Loh (Intel Malaysia), 2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT); September 5, 2018; Melaka, Malaysia Paper Presentation
- Call-for-Participation Webinar Presentation (July 28, 2017) Recording (57 min 23 sec)