Presentation (February 21, 2017). This presentation is available to both members and non-members.
Statement of Work and Project Statement
- Statement of Work (Version 1.5; February 19, 2016)
- Project Statement (Version 1.3; February 19, 2016)
- Call for Participation Webinar Presentation (March 1, 2016)
Integrated SiP packages become more useful in the electronic package solution. These push the finer and finer on the circuit pattern designs. However, optical inspection has limitation to detect the defect features: a) line width violations; b) spacing violations; c) excess copper or missing copper; d) short or open circuits; e) cuts; f) holes; g) via bottom integrity; h) line neck down; and i) micro bump shape and bump shear strength performance.
This impacts the yield performance and quality validation on the substrate/ boards which will be used for integrated SiP packages.
Inspection capability on fine line space (<20um) on the panel size substrates/ board impacts serious yield performance, which supports high I/O high bandwidth memory and other component integration; fine pitch memory or other devices.
Purpose of Project
The purpose of this project is to assess the measurement and inspection capability for fine circuit pattern substrate for high bandwidth application. This is defined in the technical gaps in the iNEMI package roadmap as “2/2 & 1/1” Design rules – Define product detail requirements and process/material equipment sets needed.
This project is phased approaches. The anticipated benefits are to provide the guideline of the inspection and metrology for the high bandwidth application substrate.
Phase 1 is to conduct the benchmarking on the metrology for the fine pitch design on the panel size areas. This includes the technology needs for the fine pitch design, inspection technique and capability for less than 5um line space traces and defect inspection, and known defect modes, yield detractors and reliability concerns.
Phase 2 is to conduct the experiment to study the metrology on line space and micro bump, and other features.
Use several TEG with design rule
AOI inspection, New techniques, Access Reliability study and FA
- Phase 2: Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology
- Phase 3: Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology
- Phase 4: Panel Level Package Fine Pitch Substrate Inspection/Metrology