Low Temperature Material for 1st Level Interconnect
Monday, February 14, 2022
Section: Packaging

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Project Leaders


Chair: Sze Pei Lim, Indium



Co-Chair: Charles Arven, IBM

Background

  • The increased size of IR detector arrays is a result of a better understanding of crystal growth techniques, better photolithography, and cleaner processing environments, all transferred from silicon foundries to the “exotic” semiconductors used for IR detectors.
  • Factors that are driving the electronics industry toward lower process temperatures are also having an impact on the 1st level interconnects that interface between the increasingly complex processors and the circuitry that relies on those processors for delivering the functionality on which modern society is now so dependent. One factor is the need to reduce the energy consumption in electronics manufacturing for economy and environmental protection.  
  • Lower process temperatures also make it possible to use cheaper, and sometimes more environmentally friendly materials, in electronic assemblies that would be degraded by the temperatures required in processes based on the current generation of lead-free solder alloys.   
  • Other temperature-related factors are warpage reduction, especially for very thin packages, and the need for a solder melting point hierarchy for multiple reflow processes. 
  • For 1st level interconnects, however, the overriding concern is the temperature sensitivity of advanced semiconductor devices. Increasing demands placed on those interconnects are forcing manufacturers to explore novel materials and processes such as transient liquid phase sintering (TLPS) materials, sinterable silver and copper pastes, and direct copper-to-copper bonding. 
  • Commonly available low melting temperature alloys such as tin-bismuth and tin-indium alloys, as well as novel low melting point alloy systems, are also under consideration.  
  • Since they play an important role in 1st level interconnects, consideration also has to be given to other assembly materials, such as conductive and non-conductive adhesives, and underfills that can be cured at lower temperatures.
     

Project Purpose

It is only relatively recently that serious consideration has been given to the use of low temperature processes for 1st level interconnect and the published literature is limited. To fill that gap iNEMI is conducting a market survey to determine current usage of low temperature materials for 1st level interconnect. The information will provide a basis for determining whether the use of low temperature materials can be extended to other advanced packaging technologies. This survey will:
  • Identify the challenges and requirements in key application sectors such as photonics, quantum computing, high performance computing, artificial intelligence, servers, sensors and LED luminaires. 
  • Gather information from substrate and material vendors on the materials that are available to meet these challenges.
The project will publish a white paper that takes into account the particular requirements of each application, recognizing the need for different materials characteristics and different measures of reliability. These needs will be matched with the materials and processes that vendors are currently offering, and will identify areas where further development is required.  The white paper will:
  • Define material properties characterization required for successful application to 1st level interconnect 
  • Propose potential application for low temp solders 
  • Identify the challenges of low temp solder use and its application
  • Provide data-based guidance on the selection of interconnect materials that can deliver an overall reduction on the processing temperature required in the 1st level construction of IC package.


Presentation

Low Temperature 1st Level Interconnect in Packaging and Its Challenges,” presented by Sze Pei Lim (Indium), iNEMI Session at ICEP, May 13, 2021  (virtual event)  
 

Contact

Masahiro Tsuriya (m.tsuriya@inemi.org)