iNEMI Warpage Characterization Project Accumulates Warpage Data to Assist in Design of Next-Generation Packaging
The ability to predict and manage package warpage at an early stage of product development is critical to ensure product yield and reliability. It is, therefore, important to characterize and monitor package dynamic warpage trends for new package technologies such as 2D, 2.5D and 3D architectures; understand the influence of new solder systems like low-temperature solder (LTS); and derive modeling techniques to enable more robust package designs for PCB assembly.
iNEMI recently completed the fourth phase of its Warpage Characteristics of Organic Packages project. Over several years, this multi-phase project has accumulated data on warpage behavior for a considerable number of packages with the objective of providing information to electronics manufacturers to refer to when designing the next generation of package technologies and developing SMT recipes. As of today, the project team has collected 15K warpage data points for 56 different packages from 16 package technology types, including 2.5D silicon interposer packages. The package warpage database created allows us to assess technology trends, identify potential risks of adopting different reflow profiles, and validate the capabilities of various simulation models to improve overall package warpage management across the electronics industry.
iNEMI hosted a session on Modeling & Simulation in Electronics Packaging at the IMPACT-IAAC conference in Taipei (October 23-25). Session speakers and participants discussed the gaps and needs for design, modelling and simulation with increasingly complex and highly integrated electronic package technologies, issuing a call to action for the electronics industry to pursue collaboration in enhancing simulation and co-design capabilities. In addition to the session, iNEMI CEO Marc Benowitz delivered a plenary address as part of the opening ceremony. His presentation — Electronics Manufacturing Challenges and Opportunities: Closing the Gaps via Collaborative Innovation — along with presentations from the iNEMI session are now available online.
iNEMI session speakers are shown here (left to right): Jim Hsu (Moldex3D), Wei Keat Loh (Intel), Haley Fu (NEMI), Yoko Fujita (Zuken), Marc Benowitz (iNEMI), and Dusan Petranovic (Mentor).
New Projects Update
5G Materials Assessment and Characterization — iNEMI hosted a brainstorming session on October 17 focusing on of 5G manufacturing challenges, specifically related to materials and processes for mmWave products. The participants, who included various sectors of the industry, highlighted the need to develop a consistent methodology for mmWave loss measurements of materials (laminate dielectrics, underfill, mold compound, thermal interface materials, etc.) to decrease development time. Possible areas identified for investigation include standard test coupon development, simulation vs. measurement correlation, fundamental process variables (e.g., during PCB/substrate fabrication), test set-up and others. A working group will be formed to explore the primary gaps and a collaborative industry model to address them. Please contact Urmi Ray (firstname.lastname@example.org) if you want to get involved.
Back End Commonality for Advanced Packaging: Large Form Factor Project — The emergence of advanced electronics packaging and adoption of heterogeneous integration and system-in-package (SiP) is leading to the use of larger packages. The larger form factors pose unique challenges in semiconductor assembly (chip-to-package) as well as PCB assembly (package-to-board). This new iNEMI project will focus on defining large form factor product-handling media (carriers, trays, etc.) for back end processes that can accurately and cost-effectively manage larger package sizes while also allowing for production flexibility and higher density. The project plans to:
Develop media handling guidelines for large-sized advanced packages (> 50mm x 50mm).
Demonstrate the cost-effectiveness of leveraging commonality
Provide input to the appropriate standards bodies regarding materials handling for large form factor packages
1st Level Interconnect Void Characterization — Flip chip packages are increasingly used in advanced electronics packaging. However, the formation of small voids (micro voids) can occur in solder-based flip chip joints during the assembly process and are a potential reliability concern, especially for applications that involve high electrical and thermal flux across the flip chip. There are currently no guidelines or standards that define an acceptable percentage of voiding or how voiding relates to assembly reliability. This new iNEMI project plans to study voiding in flip chip interconnect to determine their location and volume and to understand how voiding in 1st level interconnect affects product reliability. If you’re interested in this new project, please join one of our call-for-participation webinars on December 12 to learn more. (These sessions are open; membership is not required.) Click here for additional project information.
PCBA Cleanliness Project Studies Impact of Cleanliness on Reliability of Bottom-Terminated Components
The iNEMI PCBA Cleanliness Project recently completed a study on the impact of cleanliness on PCBAs with bottom-terminated components (BTCs). Focusing specifically on QFNs, the team evaluated different materials and test methods to identify key factors affecting reliability and evaluate trade-offs between cleanliness and performance.