Presentation: BIST Usage at the Board Level - Survey Results (July 14, 2010) (PDF file)
Project Chair: Zoe Conroy (Cisco Systems, Inc.)
An overview of the results of this project's efforts will be covered in this webinar and is open to all iNEMI members.
Presently, there are no Standard Chip level interfaces or algorithms, for BIST, which is limiting introduction at board level test. Most chip BIST routines are designed to aid IC manufacturing and the algorithms are normally not suitable to the PCB board test.
This group's objective is to develop and promote the adoption of IC BIST at the board/system level, encourage IC vendors to provide standard chip BIST interfaces and algorithms and, in addition, encourage ATE/Instrument providers to develop products based on existing related standards for BIST design. For example, an IEEE 1500/P1687 globalized Test Cost Model useful throughout the industry.
To this end, the project group’s Phase 1 efforts resulted in the development of an industry survey on the current BIST capabilities and future requirements. This Webinar will present a review of the survey’s results.For further information