Section: Packaging
1st Level Interconnect Void Characterization, Phases 1 & 2
This project is studying voids in flip chip interconnect to determine their location and volume. It will also seek to understand how voiding in 1st level interconnect affects product reliability and what level of voiding is acceptable while maintaining reliability requirements.
Fine Pitch Circuit Pattern Inspection/Metrology, Phase 1
Low Temperature Material for 1st Level Interconnect
Warpage Characterization and Management Program
This program includes the Package Warpage Prediction & Characterization Project and High Density Interconnect Socket Warpage Prediction and Characterization Project.
RDL Adhesion Strength Measurement Project
Moisture Induced Expansion Metrology for Packaging Polymetric Materials Project, Phase 1
This project will provide an experiment-based assessment of metrology options for characterization of materials expansion measurement and recommend a new metrology for moisture-induced CTE that extends swelling strain measurement capabilities beyond current temperature limits.
Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology, Phase 3
Package Warpage Prediction and Characterization, Phase 5
The Package Warpage Prediction and Characterization Project focused on development of a reliable modelling framework to predict dynamic warpage in new packages.
Wafer/Panel Level Package Flowability and Warpage
Warpage Characteristics of Organic Packages, Phase 2
New Packaging Technology Qualification Methodology
This project focused on development of a methodology for qualifying new packaging technology.