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Built-In Self-Test (BIST) Program

Chair:
Zoe Conroy, Cisco

  

Position Statement

End-of-Project Webinar

  • End-of-Project Presentation and Recording:  Built-in Self-Test (BIST), Phase 3 (Short-Term and Long-Term Strategies for Use Case Standardization); Zoe Conroy (Cisco) and Al Crouch (ASSET InterTech); May 7, 2014
  • This webinar is for iNEMI members only

Presentation from ITC 2013

Statement of Work and Project Statement

BIST Project, Phase 3 (Short-Term and Long-Term Strategies for Use Case Standardization)

Project Background

This program's focus is on “Chip” Built-in Self-Test (BIST) study and its promotion for board and system-level applications.
 
Presently, there are no Standard Chip level interfaces or algorithms for BIST, which limits the introduction of BIST at board level test. Most “chip” level BISTs are designed to aid IC manufacturing; these algorithms are often not suitable or available to run at the board level.
 
The goal of this program is to:
  • Develop and promote the adoption of IC BIST at the board/system level
  • Encourage IC vendors to provide standard chip BIST interfaces and algorithms
  • Encourage ATE/Instrument providers to develop products based on existing related standards for BIST design. For example, an IEEE 1500/P1687 globalized Test Cost Model useful throughout the industry

Project Areas / Priorities

iNEMI BIST Program consists of four phases:
  1. Survey on BIST Availability, Usage, Access at Board Level Test (Phase 1 - complete)
  2. BIST Use Case Investigation Project (Phase 2 - complete)
    Investigate and identify a “use case” to use as discussion, modeling, and development material.  Also identify main users of board BIST, definition for board BIST, and its value add.
  3. iNEMI BIST Short-Term and Long-Term Strategies for Use Case Classification Project (Phase 3)
    Investigate and identify for the "use case" as defined in the iNEMI BIST investigation (currently in sign-up)
  4. Board-Level Test Recommendations for Standardization of Component BIST (Phase 4)
Phase 2 results concluded:  (1) the ability of BIST to test the interfaces between two adjacent ASICs and (2) from an ASIC to external memory interfaces. These two use-cases will be the focus for Phase 3 work.

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