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Inspection and Reliability Study of Voids in First-Level Interconnects for Flip Chip Packages

The evolution of electronic packaging to enable 3D heterogeneous integration has led to a continuous downscaling of solder interconnects. With the emergence of packaging technologies like silicon bridges, interposers and die-to-die stacking, micro-bumps in electronic packages are getting smaller and smaller. The shrinkage of bump size to cater to higher I/Os in increasingly complex packaging design can potentially lead to weaker interconnect joints. Common defects that are evident in larger solder joints could become critical in smaller micro-bumps. One such defect is voiding. The presence of voids in small micro-bumps not only reduces solder volume and affects joint structural integrity but also restricts current flow and increases current density in the joint. Voids within flip chips also tend to grow, especially after multiple reflows. This can be a concern for certain applications that involve high electrical and thermal flux across the flip chip. Void formation can also impact electromigration in the joint which can accelerate failure.

The aim of iNEMI’s ongoing 1st Level Interconnect Void Characterization project is to study the effect of voiding in first-level micro-bumps on the joint reliability and develop guidelines regarding what type of voiding may be acceptable in certain applications. Presently, there are no industry guidelines or standards that address how voiding affects joint reliability or specifies an acceptable level of voiding. This project has two distinct phases. The first phase includes an evaluation of the capabilities of existing X-ray equipment to identify and quantify micro voids, as well as development of a process for assembling test vehicles for testing. The second phase will study the impact of such voids on electrical and mechanical reliability of the joints. This article reports on the first phase and presents a summary of how the assembly process for suitable test vehicles with relevant voiding was developed and how the test vehicles were inspected.

Kor Oon Lee (Intel), Project Chair
By Kor Oon Lee (Intel), Project Chair
on April 5, 2021 3:33:53 PM EDT
   
Inspection and Reliability Study of Voids in First-Level Interconnects for Flip Chip Packages

The evolution of electronic packaging to enable 3D heterogeneous integration has led to a continuous downscaling of solder...

Kor Oon Lee (Intel), Project Chair
By Kor Oon Lee (Intel), Project Chair
on April 5, 2021 3:33:53 PM EDT
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