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Impact of PCB Manufacturing, Design and Material on PCB Warpage

Antonio Caputo, Intel
by Antonio Caputo, Intel on June 25, 2020 10:29:38 PM EDT

The smaller form factors and finer pitches found in today’s electronic products are driving the use of smaller components and thinner PCBs [1-3], which has led to PCB warpage issues in the surface assembly process. Warpage can negatively impact yield during the SMT process when the PCB experiences peak SAC soldering temperatures in excess of 240°C, creating potential solder joint reliability issues. Design is one way to control PCB warpage, but materials, thickness, post manufacturing bake, and different PCB processing conditions can also influence warpage.

Very little work has been published evaluating the impact of fabrication on PCB warpage. iNEMI’s PCB Warpage Characterization and Minimization Project was organized to further investigate ways to control warpage. The was divided into four phases as summarized in Figure 1.

PCB_warpage_Fig1

Figure 1: iNEMI project process flow

Details of Phase 1, which included the metrology matching study, are discussed in the work by Caputo, et al [4]. This article discusses the following key findings from Phases 2-4. Parameters for the DOE legs are defined in Tables 2 and 3.

  • Phase 2 DOE: The effect of post PCB manufacturing bake on PCB warpage (i.e., Legs 1 & 2).
  • Phase 3 DOE: The effect of PCB manufacturing, thickness, and material on PCB warpage (i.e., Legs 3, 5, 7, 9, 11, 13 & 15).
  • Phase 4: Evaluate the repeatability of the results from the Phase 3 DOE by choosing two legs (Legs 9 & 11).

Experimental Set-Up

The manufacturing panel (MP) used in this work (shown in Figure 2) was ~620 mm x ~460 mm and consisted of eight shipping panels with each shipping panel having a dimension of ~79 mm x ~64 mm. Shipping panels 1, 2, 7 and 8 are corner panels, while locations 3 – 6 are center panels.

Fig2

Figure 2. PCB manufacturing layout 

 

Fig3

Figure 3. Example of one shipping panel

Figure 3 shows a 4-up shipping panel. The yellow outline represents the panel area warpage measurement for each panel, while the four red boxes represent the local area BGA warpage measurement (i.e., ~13 mm x 13 mm) for each shipping panel.
A high temperature measurement warpage measurement system/technique was used to characterize the PCB warpage. The absolute warpage value was used to represent the PCB warpage or coplanarity in this study. In order to ensure that the PCB warpage measurements across all sites were technically equivalent, a metrology matching study was performed across four test sites. This matching study found that three of the four test sites met the matching study criteria and, hence, only these three test sites were used in this project [4].

PCB design and stack-up

The project team used a single 10-layer PCB design with less than 10% copper density variation across layers, and solid outriggers. PCBs with two different stack-ups were constructed to vary the PCB thicknesses (i.e., 0.6 mm & 0.8 mm). Refer to Table 1 and Figure 4, respectively, for details.

Table 1. Summary of Copper Densities

≤ 10% Copper Balance, Solid Outrigger Copper Balance

Layer

Percent Layer Copper Density

Percent Outrigger Copper Density

1

72.9

≥ 95

2

84.4

≥ 95

3

89.2

≥ 95

4

73.1

≥ 95

5

77.9

≥ 95

6

77.3

≥ 95

7

74.1

≥ 95

8

82.9

≥ 95

9

86.1

≥ 95

10

82.6

≥ 95

 

 

Fig4aFig4b

Figure 4: Stack-up for 0.6 mm (left) and 0.8 mm thick PCBs (right)

Phase 2 DOE: Effect of Post PCB Manufacturing Bake

Phase 2 evaluated the impact of post processing bake on PCB warpage. In this portion of the DOE, the press/lamination cycle, PCB thickness and material were held constant. For Leg 2, the PCB shipping panel was exposed to a post processing bake (see Table 2).

Table 2. Summary of Phase 2 DOE Parameters

DOE Leg*

PCB Fabrication Process

PCB Material

PCB Thickness (mm)

Post Processing

1

Condition A

Mid. Tg

0.8

No

2**

Condition A

Mid. Tg

0.8

Yes

   *Testing was performed at three sites
   *The press/lamination conditions A & B for each PCB supplier are summarized in Table 4.

 

Table 4. Summary of Press/Lamination Conditions

Attribute

PCB Supplier A

PCB Supplier B

Condition A

Condition B

Condition A

Condition B

Mid. Tg

High Tg

Mid.Tg

High Tg

Mid. Tg & High Tg

Mid. Tg & High Tg

Lamination Temp. (curing) °C

>170

>190

>170

>190

170

175

Heating Rate (°C/min)

1.77

2.85

1.43

2.28

 .58 (inner layer)

 .62 (outer layer)

2.4

Cold Press Time (minutes)

40

40

70

70

40

70

Cure Time (minutes)

77

110

103

122

96

70

  Note: For Phase 4 DOE, suppliers did their best to closely match these parameters.


The Phase 3 DOE compared coplanarity at 240°C for BGAs and panels, looking at results from two different vendors (Vendor A and Vendor B). The results are summarized in Table 5.

Table 5. Summary of Results: Coplanarity at 240°C (Vendors A & B)

Coplanarity Area

Vendor A

Vendor B

Comparison (A vs B)

BGA coplanarity

More variability was observed in the BGA area coplanarity for thin (i.e., 0.6 mm) vs. thick (i.e., 0.8 mm) PCBs

The coplanarity was statistically equivalent across all legs, and minimal variability between 0.6. mm vs. 0.8 mm thick PCBs was observed

Overall, the coplanarity was statistically different between vendors, but technically equivalent (i.e., falls within ~3-sigma)

Panel area coplanarity

Panel area coplanarity showed more variability for 0.6 mm vs. 0.8 mm thick PCBs 

Panel area coplanarity across all legs was statistically equivalent (minimal variability across all legs)

Overall, the PCB manufacturing process had the greatest impact on PCB warpage


The key finding from Phase 3 was that PCB manufacturing and processing had the greatest impact on PCB warpage.

Phase 4 DOE: Repeatability of PCB Warpage Results

Based on Phase 3 findings, Vendors A & B repeated Legs 9 and 11 of the Phase 3 DOE using the same Mid Tg material, 0.6 mm PCB stack-up and design, and processing conditions (i.e., the same press/lamination conditions A & B). For this portion of the project only one test site was used for the PCB warpage measurements. Results are summarized in Table 6.

Table 6. Summary of Results: Coplanarity at 240°C – Lot 1 vs. Lot 2 (Vendors A & B)

Coplanarity Area

Vendor A

Vendor B

Comparison (A vs B)

BGA coplanarity

Some variability was observed in the BGA area coplanarity between Lot 1 vs. Lot 2

More variability was observed in the BGA area coplanarity between Lot 2 vs. Lot 1

 

There is some lot-to-lot variability

 

Panel area coplanarity

Panel area coplanarity was not repeatable and the warpage values were worse for Lot 2 

Panel area coplanarity was not repeatable and the warpage values were worse for Lot 2 

Overall, there is lot-to-lot variability and the PCB manufacturing was not repeatable.

The trend that Vendor B vs. Vendor A had better warpage results remained the same

   Lot 1 refers to the original PCB warpage data in the Phase 3 DOE
   Lot 2 refers to the new PCB warpage data collected in the Phase 4 DOE

Conclusions

iNEMI’s PCB Warpage Characterization and Minimization Project evaluated several factors to determine their effect on warpage, including PCB manufacturing, thickness of the PCB, post processing and shipping panel location within the manufacturing panel. The key findings are as follow:
  • PCB manufacturing impacts warpage
    - There was lot-to-lot variability and the warpage results were not repeatable
  • PCB thickness has impact on warpage
  • Post processing has minimal impact on PCB warpage
  • Shipping panel location within the manufacturing panel had minimal impact on PCB warpage
  • Other factors that may impact PCB warpage include:
    - Supplier experience working with PCB material
    - PCB material lot-to-lot variability
    - Variability in the press-lamination machine used
    - Localize copper balancing

New iNEMI Projects Forming

iNEMI is currently forming two new warpage-related projects: Package Warpage Prediction and Characterization and High Density Interconnect Socket Warpage Prediction and Characterization. If you’re interested in either of these projects, contact Haley Fu (haley.fu@inemi.org).


References

  1. K. Meyyappan, P. Geng and, I. Hsu, Impact of Enabling Solution Design on SLI Reliability during Temperature Cycling using Shadow Moiré Technique, ASME ITHERM’06, San Diego, 2006.
  2. M. Kurashina., et al, Precision Improvement Study of Thermal Warpage Prediction Technology for LSI Packages, 2009 Electronic Components and Technology Conference, pp. 529–534(2009).
  3. P. Hassell, Advanced Warpage Characterization: Location and Type of Displacement Can Be Equally Important as Magnitude, Pan Pacific Microelectronics Symposium Conference, February (2001).
  4. A. Caputo, S.R. Aravamudhan, H. Fu, et al, “Impact of PCB Manufacturing, Design, and Material to PCB Warpage,” IPC/APEX, San Diego, California, 2020.




 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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