PACKAGING INNOVATION MAINTAINS THE PACE OF PROGRESS AS MOORE’S LAW SCALING SLOWS
- By: iNEMI
- On: 08/09/2017 16:10:00
- In: iNEMI Blog
The 2017 iNEMI Roadmap includes a chapter on packaging and component substrates. This chapter is intended to provide focus and direction to industry, academia and government on critical technology trends and motivations for research needed to meet next-generation packaging requirements.
As demonstrated by the roadmap, the vision for electronics serving society is changing dramatically with four primary factors driving those changes: (1) the rise of the Internet of things; (2) migration of data, logic and applications to the cloud; (3) the consumerization of data generation and data access; and (4) packaging as a key to maintaining the “Moore's Law” pace of progress.
For the last 50+ years Moore's Law scaling has paced electronics industry growth, and packaging innovation will be a major enabler in maintaining the pace of progress. Historically, packaging has acted as a space and electrical transformer providing protection for the contents of the package and access for power and signals to and from the outside world. Historically innovations in packaging were focused on minimizing impact to the power, performance and latency of silicon. Packaging has come a long way from that supporting role, and is now emerging as a key product differentiator in many cases. Emerging package types such as fan-in and fan-out wafer level packaging (WLP), 2.5D and 3D integration, system in package (SiP) and heterogeneous integration (HI) represent key innovations that need to be accelerated to maintain the pace of progress.
New architectures and platforms are emerging to populate cloud infrastructures and to meet significant demand escalation for image-intensive applications, as well as data analytic-intensive applications such as virtual reality and artificial intelligence. These market drivers are forcing changes in the global network and everything connected to it. Higher performance, lower power, increased physical density of bandwidth and decreased latency will all be required from packaging at no increase in cost.
Single-chip packaging continues to improve cost and performance, supporting continued unit growth for many package types. However, Prismark Partners projects that six of the conventional package types will see a decline in unit count through 2025. These are: DIP/SOT, SO/TSOP/SOT, QFP/LCC, BOC, wire bond BGA, and wire bond SIP. These packages are being replaced with packages providing greater interconnect density between the package and the printed circuit board and lower production cost.
The quad flat no lead (QFN) packages and all WLPs show high growth. Wire bond is losing market share due to low interconnect density and high frequency limitations. The only growth in wire bond units comes from wire bond CSP (in some cases, hybrid configurations with flip chip) and chip-on-board. Both are small I/O count that do not benefit much from the higher wiring density of flip chip. Conventional single-chip and multi-chip packaging is also losing market share to SiP and 3D package architectures.
According to Prismark, the SiP unit count is forecast to grow 65% between 2015 and 2025. This compares to 45% for IC unit count. There are many technical developments needed to ensure this move to higher functional density, and greater package-level heterogeneous integration is supported by a strong reduction in cost per function while increasing the performance parameters.
The continued growth of the industry, driven by a continuous reduction in cost per function, will require new device types, new package architectures (novel 2.5D and 3D architectures, printed electronic circuits, both active and passive embedded devices), new component substrates and new assembly processes/materials, to ensure the pace of progress. 3D through-silicon via (TSV) based architectures have been available for some time but there is still limited penetration due primarily to high costs associated with TSVs. Prismark forecasts a growth rate of 20X for TSV wafers during the 2015 to 2025 period. The advantages in performance, functional density, lower power and eventually lower cost will continue to drive increases in 3D-TSV for high-performance applications.
Difficult challengesThe roadmap team identified several key challenges facing packaging technology, including:
- Power delivery and thermal management, with innovative voltage regulators/discretes, novel cooling solutions, without compromising on form factor and performance/W.
- Improving SOC-memory bandwidth to feed the enormous gains in the physical density of processor power.
- Supporting the growing IoT connectivity market and functional diversity requirements driven by “More than Moore” heterogeneous integration technologies.
- Supporting the reliability, power integrity and thermal management challenges of 2.5D/ 3D integration.
- Reducing time to market through use of SiP co-design and simulation including electrical, thermal, chemical and mechanical for the packaged device in the system.
- Improving packaging and memory support to drive the coming yottabyte (1024) level data traffic requirement.
- Managing die, package and board warpage as form factors continue to shrink with increasing integration both on the die and on package.
The emerging FOWLP, 3D stacking and SiP packaging technologies, combined with heterogeneous integration and the continued progress with homogeneous high layer count, offer a path to improve power and cost per function by 1,000 times or more over the next decade at the leading edge.
Join us for a webinar
I'll be discussing key highlights of the Packaging and Component Substrates chapter of the 2017 iNEMI Roadmap in a webinar on Wednesday, August 30. I hope you can jjoin us. Details & registration.