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Tuesday, September 21, 2021

Board Assembly Tech Topic Series: Mechanical Shock Drop Reliability of BiSn LTS, Session 1

Date(s): September 21, 2021

Time: 9:00 AM  HKT - 10:00 AM  HKT

Session 1
Tuesday, September 21, 2021 
9;00-10:00 a.m. CST (China)
9:00-10:00 p.m. EDT (Americas) on September 20
Register for this webinar (members only; requires log-in)

Session 2
Tuesday, October 12, 2021 
10:00-11:00 a.m. EDT (Americas)
4:00-5:00 p.m. CEST (Europe)
10:00-11:00 p.m. CST (China)
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Webinar Abstract: Mechanical Shock Drop Reliability of BiSn Low-Temperature Solders 

Low-temperature solders (LTS) are defined as those requiring a peak reflow temperature below 200°C. LTS technology has a burgeoning interest currently due to the manufacturing solder joint yield, economic and ecologic benefits. iNEMI initiated the BiSn-Based Low-Temperature Soldering Process and Reliability (LTSPR) project in late 2015 to study low-temperature solders in the tin-bismuth (Sn-Bi) metallurgical system. Due to the inherent brittleness of Bismuth, the mechanical shock drop reliability of Bi-Sn solder joints, particularly the large BGA solder joints, has been a major concern and detriment in the past for the development of such low-temperature solders. 
To overcome this brittleness, ductile BiSn solders and joint reinforced pastes (JRP), containing resin, were developed by the industry’s solder suppliers. The effectiveness of these newly developed solder paste was evaluated by the LTSPR project team by designing and executing three experiments, each using a different BGA package and PCB test vehicle, and shock drop test conditions, to assess mechanical shock reliability of BiSn BGA solder joints, formed with the ductile BiSn and resin-reinforced solder pastes. Results from these three experiments were published previously in three different papers at the SMTA International Conference in 2018, 2019 and 2020. This webinar will look at the results collectively from these three experiments and cull out salient conclusions. 
The effect of certain metallurgical, board design and assembly parameters on the shock drop reliability will be explained. These parameters include the bismuth content in the solder paste alloy, the printed circuit board (PCB) surface finish, the resin height surrounding the solder joints for the JRP materials, the PCB land design, and the solder joint macrostructure, whether homogeneous or heterogeneous. 

This webinar will be of interest to any engineer currently involved in the development of low-temperature bismuth-containing solders. The audience will learn how the BiSn solder joints compare for mechanical shock drop reliability with mainstream lead-free SAC305 solder joints, whether the enhancements to alloy design and the presence of resin around the PCB end of the solder joints helps strengthen them, and the failure modes observed.

About the Speakers

Raiyo F Aspandiar
Senior Packaging Engineer
Intel Corporation

Raiyo Aspandiar chairs iNEMI’s BiSn-Based Low-Temperature Soldering Process and Reliability project. Raiyo has worked at Intel Corporation at the Boards and System Assembly Hillsboro, Oregon facility since 1983. He was part of the team that introduced surface mount technology to Intel. Over the years, he has participated in the development of printed circuit boards and assembly processes for motherboards and mobile modules, which contained a myriad of packages for the Intel microprocessors, chip sets and connectors. Currently, he is working on low-temperature soldering development. 

Raiyo has published 70+ technical papers at conferences and in industry journals and is the joint holder of 17 patents in the electronics packaging and manufacturing field. He is a past member of the SMTA Board of Directors and a current member of the SMTA Technical Advisory Committee. He received the SMTA Member of Technical Distinction Award in 2009 and the SMT Founders Award in 2018. He is a graduate of Stanford University and the Indian Institute of Technology, Bombay.

Jagadeesh Radhakrishnan
Thermal/Mechanical Platform Architect
Intel Corporation

Jagadeesh Radhakrishnan is a Thermal/Mechanical Platform Architect at Intel Corporation (Folsom, California). His areas of interest include thermo-mechanical analysis, design, modeling and testing of semiconductor packaging technology for component, board and system level applications. He is an active participant in IPC/JEDEC, iNEMI and SMTA. He led the mechanical shock test and data analysis for the iNEMI LTSPR Project. Jagadeesh received his Bachelors in Technology in Mechanical Engineering from Indian Institute of Technology, Madras and Masters in Mechanical Engineering from University of Maryland (College Park), specializing in Electronic Packaging.

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