Panel Level Package Fine Pitch Substrate Inspection/Metrology Project, Phase 4

Project Leaders

Chair: Feng Xue, IBM


Co-Chair: Charles Reynolds, IBM


Co-Chair: Zhihua (Joe) Zou, Intel

Call-for-Participation Webinar

Session 1 (Americas/Europe/APAC) 
Thursday, January 20 
8:00-9:00 a.m. EST (Americas) 
2:00-3:00 p.m. CET (Europe)
10:00-11:00 p.m. JST (Japan) 
Register for this webinar 
 
Session 2 (APAC/Americas)
Friday, January 21
10:00-11:00 a.m. JST (Japan) 
5:00-6:00 p.m. PST (Americas) on Thursday, January 20
Register for this webinar
 

Statement of Work and Project Statement ​

• Statement of Work (Version 1.0; January 16, 2021)
• Project Statement (Version 1.0; January 16, 2021)

Background

 Heterogeneous SiP packages are popular as an electronic packaging solution. These packages require finer circuitry patterns designed within the substrate/interposer (lines and spaces <10um). Defect inspection and measurement capability using AOI (automatic optical inspection) on these fine pitch substrates/interposers impacts yield, throughput and reliability. At the same time, larger panel size and more layers on substrates demands increased AOI capability to accurately detect, characterize and reject the true defects without over-rejections. Finer trace width and spaces will need better AOI optics to reduce the field of view and depth of focus while addressing warpage issues and organic panel shrinkage. Therefore, it is critical to characterize the current capabilities of AOI metrologies as well as to understand the future trends in AOI measurement and inspection technology. 

Project Focus

Previous Presentations

• “Fine Pitch Circuit Pattern Inspection Capability Study for Fan-out Wafer Level Packaging,” Feng Xue, IBM, Session WA1-1: iNEMI Session, May 11, 2022, 2022 International Conference on Electronics Packaging (ICEP 2022)

Previous Projects

• Phase 1: Fine Pitch Circuit Pattern Inspection/Metrology — Conducted an industry-wide survey to assess the readiness of measurement and inspection capabilities for fine circuit pattern substrates in 2016.      

• Phase 2: Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology — Performed an AOI inspection capability study on a glass-based test vehicle and a silicon wafer-based test in 2017/2018. The test vehicles were designed with fine pitch pattern trace widths from 10um nominal down to 4um nominal, and associated defect design such as excess copper and missing copper.     

• Phase 3: Wafer/Panel Level Fine Pitch Substrate Inspection/Metrology — Conducted an AOI inspection study on an organic substrate test vehicle of the same design in 2019/2020.