Abstracts: Advanced Packaging and Its Impact on mmWave Applications



ABSTRACTS

 

The Future of Heterogeneous Integration: Challenges and Opportunities
Dr. Madhavan Swaminathan, The Pennsylvania State University

Emerging electronic systems require dense integration of many chiplets in either 2D or 3D form. The metrics for these systems will be dictated by power, performance, form factor, cost, and reliability. The complexity of these systems is expected to be large given the integration of sensing, wireless, computing, and other functionality on a single packaging platform that combines electronics and photonics together. Such systems pose immense integration challenges but also provide opportunities for innovation on several fronts that include architecture, design, thermal, materials, embedded intelligence, and many more. This presentation will provide a discussion of the state of the art and opportunities for the future. 


 

Defluxing of Copper Pillar Bumped Flip Chips 
Ravi Parthasarathy, ZESTRON Americas

Flip-chip technology has become increasingly prevalent within the electronics industry due to its lower cost, increased package density, improved performance while maintaining or improving circuit reliability, and increased I/O density.  Solder bump technology, typically used with flip-chips has proven to be challenging to manufacture and assemble below 125μm pitch. As pitch is reduced, both standoff height and joint reliability decrease, and the risk of shorts are increased. As a result, traditional solder bumps are being replaced by copper pillar technology. Used as first-level interconnect, copper pillar technology is efficient to pitches of 80 μm and appears to be promising down to pitches of 40μm and can also improve electrical performance. This technology is becoming popular since it allows for smaller devices, greater control of standoff height and reduces the number of package substrate layers which reduces cost. 

Devices utilizing copper pillar technology have more interconnects per surface area resulting in tighter pitch and lower standoff heights. As standoff height reduces, flux residues have less area to outgas during reflow. For that reason, there is a critical need to investigate the conditions that would be required to successfully remove flux residues to ensure the functionality and reliability of the final product. 

Flux residues can affect reliability, especially with respect to underfill, in two ways. First, if flux residue is present on the solder bump, substrate or die, it can significantly reduce interfacial adhesion between the underfill and the surfaces. Once the underfilled device is stressed by thermal shock, humidity or other factors, the underfill delaminates from the surface, and a gap can be detected using acoustic microscopy. Second, fluxes can affect reliability by physically impeding the flow of underfill material. Flux residue buildup in the gap between bumps or between the die and the substrate can narrow the gap to a point where the underfill cannot flow or the edges flow faster, encapsulating air and creating a void. To ensure a void-free underfill, homogenous wetting of the underfill must occur on all surfaces. If wetting is not homogeneous, voids in the uncured underfill may translate into reliability problems later. 

This presentation reports on a study that used straight DI-water and novel low-concentration alkaline cleaning agent on copper pillar bumped flip chips. The challenge was to effectively clean flux residues underneath these components. The outcome of this study could provide a benchmark for conducting further studies involving bump pitch lower than 15 μm and denser packages including 2.5Ds and 3Ds.  The cleaning assessment methodologies employed analytical/functional testing including FTIR, ion chromatography, SEM/EDX, thermal cycling (TC) test, underfill test, high temp storage life (HTSL) test and moisture sensitivity level 3 (MSL-3) testing.

NOTE: this presentation is based on a paper presented at IPC APEX 2022, co-authored by Ravi Parthasarathy and Umut Tosun, ZESTRON Corporation (Manassas, VA USA). 


 

Novel Magnetically Aligned Anisotropic Conductive Epoxy for Electronics Interconnection and Semiconductor Packaging
Madhu Stemmermann, SunRay Scientific

SunRay Scientific will present a novel, magnetically aligned anisotropic conductive epoxy, ZTACH® ACE, which provides unique electronic interconnects (ICs) and structural integrity with lower curing temperatures, no pressure, in less space and lower weight to achieve substantial improvements relative to traditional IC methodologies.  
 
ZTACH® ACE is a multifunctional interconnect material including an electromagnetic processing technology, that has been successfully developed as an alternative to traditional IC methodologies such as low temperature solder, conductive epoxy, Anisotropic Conductive Adhesive (ACA), Anisotropic Conductive Film (ACF), indium bump bonding, and wire bonding.  ZTACH® ACE consists of ferromagnetic particles randomly dispersed in an epoxy, aligned into z-axis conductive “columns” between the device and circuitry, during the cure process in the magnetic field of the ZMAG™ Pallet.  Once cured, the ferromagnetic columns are locked into place creating a low-resistance, anisotropic connection with incredible bond strength and excellent electrical insolation between columns.  Since the technology is lead-free and low energy, the integration of this material opens the possibility of “greener” electronics manufacturing and a reduced carbon footprint.  ZTACH® ACE does not require solder bumps nor patterning, eliminating costly photolithography as well as enabling the potential to bond at the wafer level vs. single die level. The material’s high mechanical strength can eliminate the need for encapsulation in many applications.  Uniquely, ZTACH® ACE integrates into Surface Mount Technology (SMT) processes for assembly, unlike the sequential assembly of components when using traditional anisotropic conductive adhesive and films.
 
ZTACH® ACE is a lightweight electrical interconnection for a variety of applications, such as flexible and stretchable LED lighting panels, first responders’ smart medical blankets, and flexible electronic performance devices.  Beyond Flexible Electronic applications, further advancements have been made in functionalizing semiconductors for varied applications.  ZTACH® ACE technology has shown over 2X smaller footprint needs than comparable wire-bonding, with thinner and higher performance than comparable flip-chip.  SunRay Scientific is currently working on prototyping ZTACH® ACE as a scalable, IC solution, demonstrating functional high density ultrafine pitch capabilities.  Successful advancement has been achieved from 250-micron pitch down to 60-micron pitch.  Proven reliability of this z-axis interconnect includes high RF bandwidth performance (1-90 GHz), excellent radiation hardness (100 Mrad), excellent cryogenic cycling temperature performance, outstanding adhesion, shear strength, high vibration resistance, and shock tolerance.  Significant reductions in the packaging time and cost can be achieved relative to standard materials and methods.


 

High Performance Materials for Advanced Packaging 
Dr. Habib Hichri

The unprecedented growth in AI and high-performance computing, combined with the emergence of chiplet-based system integration architectures is driving large package body sizes and high package interconnect densities. Insulation materials must have a lower coefficient of thermal expansion (CTE) to maintain reliable insulation and reduce stress in large packages, and a thinner insulation layer to support finer pitch copper wiring. An additional complexity is the need for high-speed signal transmission to increase bandwidth in data center, networking switch, 5G/6G data transmission and automotive infotainment applications. The polarization of an insulation layer occurs when the high-speed signal current flows through the circuit, and it causes an electrical transmission loss with high energy consumption of signals. To reduce the transmission loss, lower dielectric constant (Dk) and loss tangent (Df) insulation materials are required. Ajinomoto Build-up Film® (ABF) was developed as an insulation film over 20 years ago and has been widely used for multi-layer IC packages due to its excellent insulation reliability, good resin flow, thickness uniformity, and semi-additive process (SAP) compatibility for fine line and space formation. In this talk, we will highlight the recent development of a new class of Ajinomoto Build-up films to meet the wiring density, package reliability and high-speed signaling challenges and contribute to the advancement of next-generation packages.