Start Date: 11/28/2023 8:00 AM EST
End Date: 11/28/2023 9:00 AM EST
November 28, 2023
8:00-9:00 a.m. EST (US)
2:00-3:00 p.m. CET (Europe)
10:00-11:00 p.m. JST (Japan)
Register for this webinar
Chips and packages have different manufacturing methods and data sizes, so the design tools are also different. This webinar will introduce new software technology that can handle — in one tool —two types of design data. This technology connects design data for different technologies in a hierarchical structure and allows all data to be edited simultaneously. It also addresses the issues of designing a package that implements chiplets. This includes the challenges of large-scale design data (due to increasing nets between chips), device implementation of heterogeneous technologies with a mixture of substrate and silicon, and I/O design complexity.
About the Speaker
Kazunari Koga, Zuken Inc.
Mr. Koga began development of an LSI/package/board (LPB) co-design environment in 2007. He joined the JEITA LPB working group in 2010, and participated in the development of LPB formats, which became an IEEE standard in 2015.
He also participated in the Semiconductor Technology Academic Research Center (STARC)’s development of a design methodology 3D ICs in 2011, and with the New Energy and Industrial Technology Development Organization’s (NEDO’s) development project for the 3D integrated design and verification platform in 2013. He currently participates in the Tokyo Institute of Technology WOW Alliance which is focused on research and development of semiconductor three-dimensional stacking.