Event Calendar

Thursday, June 16, 2022

End-of-Project Webinar: 1st Level Interconnect Void Characterization, Session 2

Start Date: 6/16/2022 9:00 AM EDT
End Date: 6/16/2022 10:00 AM EDT

NC  United States 

Organization Name: iNEMI

Masahiro Tsuriya
Email: m.tsuriya@inemi.org
Phone: (984) 333-0820

End-of-Project Webinar: 1st Level Interconnect Void Characterization Project, Phase 2

Session 2 (Americas & Europe)
Thursday, June 16, 2022
9:00-10:00 a.m. EDT (Americas)
3:00-4:00 p.m. CEST (Europe)
10:00-11:00 p.m. JST (Japan)
Register for this webinar

Session 1 (APAC)
Thursday, June 16, 2022
10:00-11:00 a.m. JST (Japan)
9:00-10:00 p.m. EDT on June 15 (Americas)
Register for this webinar

About the Project
The formation of small voids can occur in solder-based flip chip joints during the assembly process and tend to grow after multiple reflows (solid-liquid-solid). This can be a concern for certain applications that involve high electrical and thermal flux across flip chip packages because the presence of a void can accelerate complete open failure due to electromigration.
Phase 2 of the 1st Level Interconnect Void Characterization project focused on understanding the potentially adverse impact of voids in first level interconnect materials on reliability of the electrical interconnect. The project team conducted experiments to understand the relationship between voids and joint reliability (electrical and mechanical) and worked on developing recommendations on acceptable voiding characteristics for flip chip interconnects.

This end-of-project webinar will present the reliability tests results for first level interconnect, performed by electromigration, temperature cycle and thermal shock testing. The presentation includes descriptions of the test packages, reliability test conditions and test data of cross-section images and EBSD data.

 Figure 1: TV samples overview


Figure 2: Example of EBSD data

Previous/Related Project Work
Phase 1 of the 1st Level Interconnect Void Characterization project studied X-ray inspection capabilities of micro voids in first level interconnect bumps. See the Phase 1 end-of-project presentation.   
This webinar is open to industry and advance registration is required (see links above). Two webinars with the same content are scheduled, so, please join whichever one fits your schedule. For additional information, contact M. Tsuriya (m.tsuriya@inemi.org).
Project Leaders:
  Kor Oon Lee. Intel
  Sze Pei Lim, Indium
  Kiyoshi Ooi, Shinko