Event Calendar

Start Date: 8/6/2024 9:00 AM EDT
End Date: 8/6/2024 10:00 AM EDT

Location:

Organization Name: iNEMI

Contact:

Abstract

With the increasing adoption of accelerated computing, AI chip makers have reached the limit of creating larger SOCs due to the scan field size of EUV (extreme ultraviolet light). SOC size will be further limited with the introduction of high NA (numerical aperture) EUV with an even-smaller scan field dimension. To enable larger chips, manufacturers are migrating to SOP (system-on-a-package).
 
The transition to SOP requires segmenting the final chip into many “chiplets / tiles” and reassembling the components using a combination of interposers, base tiles, EMIBs and substrates.  The active chiplets / tiles, such as CPU cores, GPUs, memory and IOs are tested the same as SOCs, with advanced logic testers and BIST (built in self-test).  BIST is made possible by the active silicon within the chiplets / tiles. The interposers, base tiles, EMIBs and substrates, which are the building blocks of SOP, lack the active silicon to make traditional testing possible.  To test these foundational building blocks of SOP, massive electrical contacting arrays of probes have been used. The electrical test method using contacting arrays is slow, expensive, inflexible, and worst of all damages the device under test (DUT). To enable the testing of SOP building blocks, Applied Materials’ Yield Technology Group (YTG) has developed a non-contacting electron beam tester. This presentation will introduce the Applied Materials damage-free electron beam testing method to ensure high yield of the SOP building blocks.
 

About the Speaker

 
Peter D. Nunan, General Manager Emeritus
Yield Technology Group, Display & Flexible Technology Group
Applied Materials, Inc.
Peter D. Nunan spent 30+ years in semiconductor yield improvement. Starting at Bell Laboratories in 1979, he worked on semiconductor yield equipment from 1998 to 2014. In 2014, he assumed the role of General Manager of Applied Materials Display Yield Technology Group (2014 to 2024). The stated objective of YTG is to bring semiconductor yield methods and equipment to the display and advanced packaging industries. The group’s goal is to enable display and advanced packaging manufacturers to develop and produce advanced displays, interposers and substrates. Prior to joining Applied Materials Display Group, Peter held various positions within the semiconductor industry, including Vice President of Varian Semiconductor Technology Development and Vice President-General Manager of KLA-Tencor’s Professional Services Division.
 
Peter holds a Bachelor of Science degree in Engineering Physics and a Master of Science in Electrical Engineering from Lehigh University.
 
 

Registration

 
This webinar is open to industry; advance registration is required (see link below). If you have any questions or need additional information, please contact Masahiro Tsuriya (m.tsuriya@inemi.org).
 
 
August 6, 2024
9:00-10:00 a.m. EDT (Americas)
3:00-4:00 p.m. CEST (Europe)
10:00-11:00 p.m. JST (Japan)
Register for this webinar