Event Calendar

Start Date: 2/20/2024 8:00 AM EST
End Date: 2/20/2024 9:00 AM EST

About the Webinar

Guest Speakers:

• Dr. Dilan Seneviratne, Intel Corporation
• Dr. Gang Duan, Intel Corporation

This webinar is free and open to industry; advance registration is required.

February 20, 2024
8:00-9:00 a.m. EST (US)
2:00-3:00 CET (Europe)
10:00-11:00 p.m. JST (Japan)
Register now
 

Abstract

The age of heterogenous chiplet integration has arrived. Heterogeneous integration through advanced packaging has become a crucial product performance enabler through on-package integration of chiplets with various functionalities and IP blocks. To meet future scaling needs, package substrate technologies must evolve beyond the capabilities of current organic substrates. Glass substrates have the mechanical, physical, electrical, and optical properties that allow for higher computing performance, better interconnect scaling, more design flexibilities, and larger form factor chiplet complex assemblies in a single package. 

Intel is one of the first to achieve glass substrates for advanced packaging solutions and is in progress to deliver this breakthrough innovation to the market in the second half of this decade. In this presentation, we provide a status overview of Intel’s glass core substrate package technologies and advancements needed by the industry to enable high-performance computing needs through advanced packaging.
 

About the Speakers

Dilan Seneviratne, PhD
Intel Corporation
Dilan Seneviratne is a Principal Engineer and Director of Dielectrics and Surface Prep Area within Intel’s Substrate Packaging Technology Development organization. He has worked on multiple generations of Intel’s substrate research and development programs since the 45nm technology node. He has been instrumental in enabling multiple generations of substrate dielectric materials for conventional and high-speed applications along with key processes in support of Intel’s IC substrates.  He continues to drive future roadmaps critical for heterogenous integration and advance packaging. 

Prior to joining Intel, Dilan was a researcher working in ceramics, MEMS and silicon photonics. He has a Ph.D. in Materials Science and Engineering from Massachusetts Institute of Technology and a bachelor’s degree from Imperial College, London, U.K.

Gang Duan, PhD
Intel Corporation
Gang Duan is a Principal Engineer and Area Manager / Engineering Director for Backend area in the Substrate Packaging TD organization within Assembly Test TD at Intel. He is responsible for developing EMIB / EMIB-TSV die embedding, as well as HDI substrate backend process, equipment, and materials technologies. 

Gang holds 250+ USA issued / pending patents in the field of packaging processes / architectures / materials. He has authored 35+ technical papers in highly regarded academic journals and industry conferences. Gang is a Senior member of IEEE, and a member of ECTC's 2024 Interconnections Technical Committee. He received his Ph.D. in Materials Science, and his M.S. in Electrical Engineering from the California Institute of Technology (Caltech).
 

Registration

This webinar is open to industry; advance registration is required (see link below). If you have any questions or need additional information, please contact Masahiro Tsuriya (m.tsuriya@inemi.org).

February 20, 2024
8:00-9:00 a.m. EST (US)
2:00-3:00 CET (Europe)
10:00-11:00 p.m. JST (Japan)
Register now