QFN Package Board Level Reliability Project
Project Leader: Richard Coyle (Nokia Bell Labs)
Statement of Work and Project Statement
There are an increasing number of IC devices being packaged in no-lead packages such as the Quad Flat No-Lead (QFN) or Micro-Lead Frame (MLF) packages. These packages initially were developed as a low form factor package for hand-held consumer electronic devices. They have additional advantages such as minimizing board real estate usage, excellent thermal management characteristics, potentially better electrical performance, and generally lower cost than competitive packaging. In very recent years, the usage of QFN packages has expanded into telecom and automotive applications, where long term board level reliability (BLR) requirements for thermal fatigue resistance are more demanding compared to consumer applications.
Failure resulting from solder thermal fatigue is a principal concern due to the inherently high coefficient of thermal expansion (CTE) mismatch, low solder standoff, and non-compliant peripheral interconnects of the non-leaded package. These packages also present solder assembly challenges that can impact BLR further. The packaging technology is evolving in the direction of larger body size, finer pitch, and higher pin count, all of which increase reliability risks and assembly challenges.
QFN package usage continues to be dominated by high-volume manufacturers of consumer electronics, and much of the existing reliability test data have been generated to address those requirements. Consequently, thermal cycling data are lacking for characterizing longer product lifetimes and more aggressive use environments, particularly for thicker printed circuit boards typical of higher reliability applications.
The focus of this project is to isolate the effects of several key parameters on thermal cycle reliability of a large body QFN package. To accomplish this, a test vehicle will be designed to incorporate several design features, including the ability to evaluate effect of body size, die size, and pitch. Selected variables will be evaluated using a phased approach to close information gaps and minimize the complexity of each test. See the SOW for a description of Phase 1 work and suggestions for work in subsequent phases.
For Additional InformationMasahiro Tsuriya