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Presentations from Substrate & Package Technology Workshop
These are presentations from the iNEMI Substrate & Package Technology Workshop: Road to Integrated SiP Package Technology Innovation, hosted by IBM in Singapore (May 26-27, 2016).
These presentations are available to workshop attendees and iNEMI members only. If you are an iNEMI member, please log into your account or create a web account to view. If you attended the workshop and need these presentations, please contact dtaylor@inemi.org.
Workshop Program
Includes Agenda, Speaker Bios/Abstracts
iNEMI & Workshop Overview
Haley Fu, Managing Director, iNEMI
An Overview of Market and Technology Trends in the Advanced Packaging Ecosystem
Santosh KUMAR, Sr Analyst, Yole Developpement
Package Scaling and Heterogeneous Integration
Wei Keat Loh, Sr Technology Development, Engineering Manager, ATTD, Intel
Solder Alloy Options for the Semiconductor and PCB Assembly
Sze Pei Lim, Regional Product Manager – Semiconductor, Indium Corp.
Device Embedded Package MCeP for SiP Application
Tetsuya Koyama, Manager of Interconnect Technology Development, Shinko
Wafer/Panel Level Encapsulation - an Alternative Format for Plastic Packaging: Its Challenges and Solutions
Eric Kuah, VP, Technology Encapsulation, Solutions Group, ASM Singapore
An End User's Perspective on Qualifying New Packaging Technologies
Curtis Grosskopf, Senior Engineer, System Supply Chain Engineering, IBM
eWLB /FO-WLP: Present and Future of Advanced Wafer Level Packaging Technology
SW Yoon, Director / Products & Technology Marketing, STATS ChipPAC
Advanced Substrate Materials for Next Generation Low CTE/Thinner Package with High Reliability
Hiroaki Fujita, Hitachi Chemical
Enabling Ultimate Miniaturization and Customization with the Latest SiP Module Technology
L.C. Tan, Head, Assembly Process Innovation, NXP Semiconductors
High End Organic Substrate Direction
Koichi Nonomura, Manager of FCBGA Product Engineering, KYOCERA
Innovative SiP Technology
Stanley Wu, Technical Manager, ASE
Heterogeneous Integration Platforms for Mobile and IoT
Surya Bhattacharya, Director, A*STAR Institute of Microelectronics (IME)*
Molded Interconnect Substrate (MIS)
ASM Pacific Technology
Workshop Program
Includes Agenda, Speaker Bios/Abstracts
iNEMI & Workshop Overview
Haley Fu, Managing Director, iNEMI
An Overview of Market and Technology Trends in the Advanced Packaging Ecosystem
Santosh KUMAR, Sr Analyst, Yole Developpement
Package Scaling and Heterogeneous Integration
Wei Keat Loh, Sr Technology Development, Engineering Manager, ATTD, Intel
Solder Alloy Options for the Semiconductor and PCB Assembly
Sze Pei Lim, Regional Product Manager – Semiconductor, Indium Corp.
Device Embedded Package MCeP for SiP Application
Tetsuya Koyama, Manager of Interconnect Technology Development, Shinko
Wafer/Panel Level Encapsulation - an Alternative Format for Plastic Packaging: Its Challenges and Solutions
Eric Kuah, VP, Technology Encapsulation, Solutions Group, ASM Singapore
An End User's Perspective on Qualifying New Packaging Technologies
Curtis Grosskopf, Senior Engineer, System Supply Chain Engineering, IBM
eWLB /FO-WLP: Present and Future of Advanced Wafer Level Packaging Technology
SW Yoon, Director / Products & Technology Marketing, STATS ChipPAC
Advanced Substrate Materials for Next Generation Low CTE/Thinner Package with High Reliability
Hiroaki Fujita, Hitachi Chemical
Enabling Ultimate Miniaturization and Customization with the Latest SiP Module Technology
L.C. Tan, Head, Assembly Process Innovation, NXP Semiconductors
High End Organic Substrate Direction
Koichi Nonomura, Manager of FCBGA Product Engineering, KYOCERA
Innovative SiP Technology
Stanley Wu, Technical Manager, ASE
Heterogeneous Integration Platforms for Mobile and IoT
Surya Bhattacharya, Director, A*STAR Institute of Microelectronics (IME)*
Molded Interconnect Substrate (MIS)
ASM Pacific Technology