Abstract

One of the greatest challenges in heterogeneous integration of different types of silicon, memory, and other extended processing units (XPUs) is in attaching these various types of chips to the package in a reliable way. Key modulators for this reliability are the maximum temperature that the silicon chip experiences during assembly bonding processes, interaction with chip warpage, and solder joint reliability.

To address these challenges, INEMI’s Low-Temperature Material Discovery and Characterization for First-Level Interconnect Project has conducted simulation studies of novel low-temperature solder materials, including SAC305, eutectic SnBi and SnBiCuNi, using solder package structures with solder sphere and Cu pillar interconnections.

The webinar will share results from the team’s modeling and simulation of first-level interconnection reliability, including bump collapse simulation, thermal electronical simulation and electromigration simulation. It will also talk about future plans for the project.

Webinar Speakers

	Russel Kastberg (IBM), Project Co-Chair    Webinar moderator
	Gokhale Shripad (Intel), Project Chair    Topic: bump collapse modeling and simulation results
	Kei Murayama (Shinko)    Topic: electromigration modeling and simulation results
	Yasuharu Yamada (IBM)    Topic: thermal mechanical modeling and simulation results

Registration

This webinar is open to industry; advance registration is required (see link below). You will need to log into your web account (free to members and non-members) to register. If you do not have a current web account, please create one and set up your profile.  If you have any questions or need additional information, please contact Masahiro Tsuriya ([email protected]).

Thursday, June 19, 2025
10:00-11:00 a.m. JST (Japan)
9:00-10:00 p.m. EDT on Thursday, June 18 (U.S. & Canada)