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2026 Council of Members Meeting

30 June 2026

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PCB Connector Footprint Tolerance


End-of-Project Webinar

Thursday, October 28, 2024 11:00 a.m. – 12:00 p.m. EDT (Americas)4:00-5:00 p.m. CET (Europe)
Register for this webinar

 

Statement of Work & Project Statement

Statement of Work v1.3 (March 24, 2023)
Project Statement v1.2 (March 24, 2023)

 

Background

I/O bandwidth is more than doubling every three years. While card electromechanical (CEM) compliant connectors remain at 1.0 mm pitch, newer form factors, as detailed in specifications such as SFF TA-1002, reduce connector pitch to 0.6 mm.  This combination of size reduction and bandwidth increase is driving new and tighter PCB/FPC (flexible printed circuit) design requirements that may exceed the capability of fabrication processes used for previous generations of I/O connector interfaces. In short, connector land pattern tolerances drive process requirements not previously needed. Identifying which processes are needed, conducting risk assessment, and meeting product quality requirements demands an understanding of complex process interactions.
 
It is against this background that an informed and comprehensive study is required to provide product designers using these high I/O bandwidth connectors with the information they need to successfully build products at a predictable quality level.
 

Project Focus

This is a fast-turnaround project that will: 

  • Determine standards and footprints to be considered  
  • Determine manufacturing requirements to be considered
  • Determine PCB/FPC supplier capability and capacity
  • Develop quality assessment inputs
  • Develop recommendations for quality control
     

Project Benefits & Value to Industry

  • Enable product designers using high I/O bandwidth connector footprints to understand which manufacturing processes are needed for their products through risk assessments and enable PCB suppliers to meet product quality requirements
  • Provide better understanding of risks associated with high I/O bandwidth connector footprints
  • Reduce product qualification costs and associated time to market
     

Outcome of Project

  • Characterize industry capability and capacity for input into risk assessments
  • Produce a document that provides the inputs needed to match risk and quality with product requirements to enable PCB fabricators to create products that meet design intent
     

Presentations

Call-for-participation webinar presentation (includes link to recorded webinar) May 9 & 10, 2023

Contact

Mark Schaffer
[email protected]

Project Leaders

Joe Fuller, Intel

Chandra Krishnaswamy, Dell
Sudip Thomas, Intel

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